mpc456

Note that this grouping of the instructions does not indicate which execution unit executes a particular
instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. The PowerPC
architecture uses instructions that are four bytes long and word-aligned. It provides for byte, half-word, and
word operand loads and stores between memory and a set of 32 GPRs. It also provides for word and doubleword

operand loads and stores between memory and a set of 32 floating-point registers (FPRs).
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register, modified,
and then written back to the target location with distinct instructions.
PowerPC processors follow the program flow when they are in the normal execution state. However, the
flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous
event. Either kind of exception may cause one of several components of the system software to be invoked.
3.3.1.2 Calculating Effective Addresses
The effective address (EA) is the 32-bit address computed by the processor when executing a memory
access or branch instruction or when fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
• EA = (rA|0) + offset (including offset = 0) (register indirect with immediate index)
• EA = (rA|0) + rB (register indirect with index)
These simple addressing modes allow efficient address generation for memory accesses. Calculation of the
effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address, the memory operand is considered to wrap around from the maximum effective
address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic.
A carry from bit 0 is ignored in 32-bit implementations.
3.3.2 PowerPC 603 Microprocessor Instruction Set
The 603 instruction set is defined as follows:
• The 603 provides hardware support for all 32-bit PowerPC instructions.
• The 603 provides two implementation-specific instructions used for software table search
operations following TLB misses:
– Load Data TLB Entry (tlbld)
– Load Instruction TLB Entry (tlbli)
• The 603 implements the following instructions which are defined as optional by the PowerPC
architecture:
– External Control In Word Indexed (eciwx)
– External Control Out Word Indexed (ecowx)
– Floating Select (fsel)
– Floating Reciprocal Estimate Single-Precision (fres)
– Floating Reciprocal Square Root Estimate (frsqrte)
– Store Floating-Point as Integer Word (stfiwx)
18 PowerPC 603 RISC Microprocessor Technical Summary
3.4 Cache Implementation
The following subsections describe the PowerPC architecture’s treatment of cache in general, and the 603-
specific implementation, respectively.
3.4.1 PowerPC Cache Characteristics
The PowerPC architecture does not define hardware aspects of cache implementations. For example, some
PowerPC processors, including the 603, have separate instruction and data caches (Harvard architecture),
while others, such as the PowerPC 601™ microprocessor, implement a unified cache.
PowerPC microprocessors control the following memory access modes on a page or block basis:
• Write-back/write-through mode
• Cache-inhibited mode
• Memory coherency
Note that in the 603, a cache line is defined as eight words. The VEA defines cache management instructions
that provide a means by which the application programmer can affect the cache contents.
3.4.2 PowerPC 603 Microprocessor Cache Implementation
The 603 has two 8-Kbyte, two-way set-associative (instruction and data) caches. The caches are physically
addressed, and the data cache can operate in either write-back or write-through mode as specified by the
PowerPC architecture.
The data cache is configured as 128 sets of 2 lines each. Each line consists of 32 bytes, two state bits, and
an address tag. The two state bits implement the three-state MEI (modified/exclusive/invalid) protocol. Each
line contains eight 32-bit words. Note that the PowerPC architecture defines the term block as the cacheable
unit. For the 603, the block size is equivalent to a cache line. A block diagram of the data cache organization
is shown in Figure 3.
The instruction cache also consists of 128 sets of 2 lines, and each line consists of 32 bytes, an address tag,
and a valid bit. The instruction cache may not be written to except through a line fill operation. The
instruction cache is not snooped, and cache coherency must be maintained by software. A fast hardware
invalidation capability is provided to support cache maintenance. The organization of the instruction cache
is very similar to the data cache shown in Figure 3.
Each cache line contains eight contiguous words from memory that are loaded from an 8-word boundary
(that is, bits A27–A31 of the effective addresses are zero); thus, a cache line never crosses a page boundary.
Misaligned accesses across a page boundary can incur a performance penalty.
The 603’s cache lines are loaded in four beats of 64 bits each. The burst load is performed as “critical double
word first.” The cache that is being loaded is blocked to internal accesses until the load completes. The
critical double word is simultaneously written to the cache and forwarded to the requesting unit, thus
minimizing stalls due to load delays.
To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the
603 implements the MEI protocol. These three states, modified, exclusive, and invalid, indicate the state of
the cache block as follows:
• Modified—The cache line is modified with respect to system memory; that is, data for this address
is valid only in the cache and not in system memory.
• Exclusive—This cache line holds valid data that is identical to the data at this address in system
memory. No other cache has this data.
• Invalid—This cache line does not hold valid data.