1.6 Processor Bus Interface

1.6 Processor Bus Interface
Because the caches on the 603 are on-chip, write-back caches, the predominant type of transaction for most
applications is burst-read memory operations, followed by burst-write memory operations, single-beat
(noncacheable or write-through) memory read and write operations, and direct-store interface operations.
Additionally, there can be address-only operations, variants of the burst and single-beat operations, (for
example, global memory operations that are snooped and atomic memory operations), and address retry
activity (for example, when a snooped read access hits a modified line in the cache).
Memory accesses can occur in single-beat (1–8 bytes) and four-beat burst (32 bytes) data transfers when the
bus is configured as 64 bits, and in single-beat (1–4 bytes), two-beat (8 bytes), and eight-beat (32 bytes) data

transfers when the bus is configured as 32 bits. The address and data buses operate independently to support
pipelining and split transactions during memory accesses. The 603 can pipeline its own transactions to a
depth of one level.
Access to the system interface is granted through an external arbitration mechanism that allows devices to
compete for bus mastership. This arbitration mechanism is flexible, allowing the 603 to be integrated into
systems that implement various fairness and bus parking procedures to avoid arbitration overhead.
Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and
multiple instructions, do not necessarily complete in the order they begin—maximizing the efficiency of the
bus without sacrificing coherency of the data. The 603 allows read operations to precede store operations
(except when a dependency exists). Because the processor can dynamically optimize run-time ordering of
load/store traffic, overall performance is improved.
1.7 System Support Functions
The 603 implements several support functions that include power management, time base/decrementer
registers for system timing tasks, an IEEE 1149.1(JTAG)/common on-chip processor (COP) test interface,
and a phase-locked loop (PLL) clock multiplier. These system support functions are described in the
following subsections.
1.7.1 Power Management
The 603 provides four power modes selectable by setting the appropriate control bits in the machine state
register (MSR) and hardware implementation register 0 (HID0) registers. The four power modes are as
follows:
10 PowerPC 603 RISC Microprocessor Technical Summary
• Full-power–This is the default power state of the 603. The 603 is fully powered and the internal
functional units are operating at the full processor clock speed. If the dynamic power management
mode is enabled, functional units that are idle will automatically enter a low-power state without
affecting performance, software execution, or external hardware.
• Doze–All the functional units of the 603 are disabled except for the time base/decrementer registers
and the bus snooping logic. When the processor is in doze mode, an external asynchronous
interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine
check brings the 603 into the full-power state. The 603 in doze mode maintains the PLL in a fully
powered state and locked to the system external clock input (SYSCLK) so a transition to the fullpower
state takes only a few processor clock cycles.
• Nap–The nap mode further reduces power consumption by disabling bus snooping, leaving only the
time base register and the PLL in a powered state. The 603 returns to the full-power state upon
receipt of an external asynchronous interrupt, a system management interrupt, a decrementer
exception, a hard or soft reset, or a machine check input (MCP). A return to full-power state from
a nap state takes only a few processor clock cycles.
• Sleep–Sleep mode reduces power consumption to a minimum by disabling all internal functional
units, after which external system logic may disable the PLL and SYSCLK. Returning the 603 to
the full-power state requires the enabling of the PLL and SYSCLK, followed by the assertion of an
external asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine
check input (MCP) signal after the time required to relock the PLL.
1.7.2 Time Base/Decrementer
The time base is a 64-bit register (accessed as two 32-bit registers) that is incremented once every four bus
clock cycles; external control of the time base is provided through the time base enable (TBEN) signal. The
decrementer is a 32-bit register that generates a decrementer exception after a programmable delay. The
contents of the decrementer register are decremented once every four bus clock cycles, and the decrementer
exception is generated as the count passes through zero.
1.7.3 IEEE 1149.1 (JTAG)/COP Test Interface
The 603 provides IEEE 1149.1 and COP functions for facilitating board testing and chip debug. The IEEE
1149.1 test interface provides a means for boundary-scan testing the 603 and the board to which it is
attached. The COP function shares the IEEE 1149.1 test port, provides a means for executing test routines,
and facilitates chip and software debugging.
1.7.4 Clock Multiplier
The internal clocking of the 603 is generated from and synchronized to the external clock signal, SYSCLK,
by means of a voltage-controlled oscillator-based PLL. The PLL provides programmable internal processor
clock rates of 1x, 2x, 3x, and 4x multiples of the externally supplied clock frequency. The bus clock is the
same frequency and is synchronous with SYSCLK.
Part 2 Levels of the PowerPC Architecture
The PowerPC architecture consists of the following layers, and adherence to the PowerPC architecture can
be measured in terms of which of the following levels of the architecture is implemented:
• PowerPC user instruction set architecture (UISA)—Defines the base user-level instruction set, userlevel
registers, data types, floating-point exception model, memory models for a uniprocessor
environment, and programming model for a uniprocessor environment.
PowerPC 603 RISC Microprocessor Technical Summary 11
• PowerPC virtual environment architecture (VEA)—Describes the memory model for a
multiprocessor environment, defines cache control instructions, and describes other aspects of
virtual environments. Implementations that conform to the VEA also adhere to the UISA, but may
not necessarily adhere to the OEA.
• PowerPC operating environment architecture (OEA)—Defines the memory management model,
supervisor-level registers, synchronization requirements, and the exception model.
Implementations that conform to the OEA also adhere to the UISA and the VEA.
The PowerPC architecture allows a wide range of designs for such features as cache and system interface
implementations.
Part 3 PowerPC 603 Microprocessor: Implementation
The PowerPC architecture is derived from the IBM POWER Architecture™ (Performance Optimized with
Enhanced RISC architecture). The PowerPC architecture shares the benefits of the POWER architecture
optimized for single-chip implementations. The PowerPC architecture design facilitates parallel instruction
execution and is scalable to take advantage of future technological gains.
This section describes the PowerPC architecture in general, and specific details about the implementation
of the 603 as a low-power, 32-bit member of the PowerPC processor family.
• Features—Section 3.1, “Features,” describes general features that the 603 shares with the PowerPC
microprocessor family.
• Registers and programming model—Section 3.2, “PowerPC Registers and Programming Model,”
describes the registers for the operating environment architecture common among PowerPC
processors and describes the programming model. It also describes the additional registers that are
unique to the 603.
• Instruction set and addressing modes—Section 3.3, “Instruction Set and Addressing Modes,”
describes the PowerPC instruction set and addressing modes for the PowerPC operating
environment architecture, and defines and describes the PowerPC instructions implemented in the
603.
• Cache implementation—Section 3.4, “Cache Implementation,” describes the cache model that is
defined generally for PowerPC processors by the virtual environment architecture. It also provides
specific details about the 603 cache implementation.
• Exception model—Section 3.5, “Exception Model,” describes the exception model of the PowerPC
operating environment architecture and the differences in the 603 exception model.
• Memory management—Section 3.6, “Memory Management,” describes generally the conventions
for memory management among the PowerPC processors. This section also describes the 603’s
implementation of the 32-bit PowerPC memory management specification.
• Instruction timing—Section 3.7, “Instruction Timing,” provides a general description of the
instruction timing provided by the superscalar, parallel execution supported by the PowerPC
architecture and the 603.
• System interface—Section 3.8, “System Interface,” describes the signals implemented on the 603.
3.1 Features
The 603 is a high-performance, superscalar PowerPC microprocessor. The PowerPC architecture allows
optimizing compilers to schedule instructions to maximize performance through efficient use of the
PowerPC instruction set and register model. The multiple, independent execution units allow compilers to
optimize instruction throughput. Compilers that take advantage of the flexibility of the PowerPC
architecture can additionally optimize system performance of the PowerPC processors.
12 PowerPC 603 RISC Microprocessor Technical Summary
Specific features of the 603 are listed in Section 1.1, “PowerPC 603 Microprocessor Features.”
3.2 PowerPC Registers and Programming Model
The PowerPC architecture defines register-to-register operations for most computational instructions.
Source operands for these instructions are accessed from the registers or are provided as immediate values
embedded in the instruction opcode. The three-register instruction format allows specification of a target
register distinct from the two source operands. Load and store instructions transfer data between registers
and memory.
PowerPC processors have two levels of privilege—supervisor mode of operation (typically used by the
operating system) and user mode of operation (used by the application software). The programming models
incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs), and several miscellaneous registers. Each
PowerPC microprocessor also has its own unique set of hardware implementation (HID) registers.
Having access to privileged instructions, registers, and other resources allows the operating system to
control the application environment (providing virtual memory and protecting operating-system and critical
machine resources). Instructions that control the state of the processor, the address translation mechanism,
and supervisor registers can be executed only when the processor is operating in supervisor mode.
The following sections summarize the PowerPC registers that are implemented in the 603.
3.2.1 General-Purpose Registers (GPRs)
The PowerPC architecture defines 32 user-level, general-purpose registers (GPRs). These registers are either
32 bits wide in 32-bit PowerPC microprocessors and 64 bits wide in 64-bit PowerPC microprocessors. The
GPRs serve as the data source or destination for all integer instructions.
3.2.2 Floating-Point Registers (FPRs)
The PowerPC architecture also defines 32 user-level, 64-bit floating-point registers (FPRs). The FPRs serve
as the data source or destination for floating-point instructions. These registers can contain data objects of
either single- or double-precision floating-point formats.
3.2.3 Condition Register (CR)
The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the results of certain
operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and
provide a mechanism for testing and branching.
3.2.4 Floating-Point Status and Control Register (FPSCR)
The floating-point status and control register (FPSCR) is a user-level register that contains all exception
signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance
with the IEEE 754 standard.
3.2.5 Machine State Register (MSR)
The machine state register (MSR) is a supervisor-level register that defines the state of the processor. The
contents of this register are saved when an exception is taken and restored when the exception handling
completes. The 603 implements the MSR as a 32-bit register; 64-bit PowerPC processors implement a 64-
bit MSR.
PowerPC 603 RISC Microprocessor Technical Summary 13
3.2.6 Segment Registers (SRs)
For memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit segment registers
(SRs). To speed access, the 603 implements the segment registers as two arrays; a main array (for data
memory accesses) and a shadow array (for instruction memory accesses). Loading a segment entry with the
Move to Segment Register (mtsr) instruction loads both arrays.
3.2.7 Special-Purpose Registers (SPRs)
The PowerPC operating environment architecture defines numerous special-purpose registers that serve a
variety of functions, such as providing controls, indicating status, configuring the processor, and performing
special operations. During normal execution, a program can access the registers, shown in Figure 2,
depending on the program’s access privilege (supervisor or user, determined by the privilege-level (PR) bit
in the MSR). Note that registers such as the GPRs and FPRs are accessed through operands that are part of
the instructions. Access to registers can be explicit (that is, through the use of specific instructions for that
purpose such as Move to Special-Purpose Register (mtspr) and Move from Special-Purpose Register
(mfspr) instructions) or implicit, as the part of the execution of an instruction. Some registers are accessed
both explicitly and implicitly
In the 603, all SPRs are 32 bits wide.
3.2.7.1 User-Level SPRs
The following 603 SPRs are accessible by user-level software:
• Link register (LR)—The link register can be used to provide the branch target address and to hold
the return address after branch and link instructions. The LR is 32 bits wide in 32-bit
implementations.
• Count register (CTR)—The CTR is decremented and tested automatically as a result of branch-andcount
instructions. The CTR is 32 bits wide in 32-bit implementations.
• Integer exception register (XER)—The 32-bit XER contains the summary overflow bit, integer
carry bit, overflow bit, and a field specifying the number of bytes to be transferred by a Load String
Word Indexed (lswx) or Store String Word Indexed (stswx) instruction.
3.2.7.2 Supervisor-Level SPRs
The 603 also contains SPRs that can be accessed only by supervisor-level software. These registers consist
of the following:
• The 32-bit DSISR defines the cause of data access and alignment exceptions.
• The data address register (DAR) is a 32-bit register that holds the address of an access after an
alignment or DSI exception.
• Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for
causing a decrementer exception after a programmable delay.
• The 32-bit SDR1 specifies the page table format used in virtual-to-physical address translation for
pages. (Note that physical address is referred to as real address in the architecture specification.)
• The machine status save/restore register 0 (SRR0) is a 32-bit register that is used by the 603 for
saving the address of the instruction that caused the exception, and the address to return to when a
Return from Interrupt (rfi) instruction is executed.
• The machine status save/restore register 1 (SRR1) is a 32-bit register used to save machine status
on exceptions and to restore machine status when an rfi instruction is executed.
• The 32-bit SPRG0–SPRG3 registers are provided for operating system use.
14 PowerPC 603 RISC Microprocessor Technical Summary
• The external access register (EAR) is a 32-bit register that controls access to the external control
facility through the External Control In Word Indexed (eciwx) and External Control Out Word
Indexed (ecowx) instructions.
• The time base register (TB) is a 64-bit register that maintains the time of day and operates interval
timers. The TB consists of two 32-bit fields—time base upper (TBU) and time base lower (TBL).
• The processor version register (PVR) is a 32-bit, read-only register that identifies the version
(model) and revision level of the PowerPC processor.
• Block address translation (BAT) arrays—The PowerPC architecture defines 16 BAT registers,
divided into four pairs of data BATs (DBATs) and four pairs of instruction BATs (IBATs). See
Figure 2 for a list of the SPR numbers for the BAT arrays.
The following supervisor-level SPRs are implementation-specific to the 603:
• The DMISS and IMISS registers are read-only registers that are loaded automatically upon an
instruction or data TLB miss.
• The HASH1 and HASH2 registers contain the physical addresses of the primary and secondary
page table entry groups (PTEGs).
• The ICMP and DCMP registers contain a duplicate of the first word in the page table entry (PTE)
for which the table search is looking.
• The required physical address (RPA) register is loaded by the processor with the second word of the
correct PTE during a page table search.
• The hardware implementation (HID0) register provides means for enabling the 603’s checkstops
and features.
• The instruction address breakpoint register (IABR) is loaded with an instruction address that is
compared to instruction addresses in the dispatch queue. When an address match occurs, an
instruction address breakpoint exception is generated.
Figure 2 shows all the 603 registers available at the user and supervisor level. The numbers to the right of
the SPRs indicate the number that is used in the syntax of the instruction operands to access the register.