DMA to PLB 4 Controller

DMA to PLB4 Controller
This DMA controller provides a DMA interface dedicated to the USB 2.0 device ports and the 128-bit PLB.
Features include:
• 4 independent channels supporting internal USB 2.0 Device endpoints 1 and 2
• Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers
• Scatter/gather capability
• 128-byte buffer with programmable thresholds
Serial Ports (UART)
Features include:

• Up to four ports in the following combinations:
– One 8-pin
– Two 4-pin
– One 4-pin and two 2-pin
– Four 2-pin
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA function on PLB 64
IIC Bus Interface
Features include:
• Two IIC interfaces provided
• Support for Philips® Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
• Includes an integrated boot-strap controller (BSC) that is multiplexed with the IIC0 interface

External Peripheral Bus Controller (EBC) The PowerPC 440 EP

External Peripheral Bus Controller (EBC)
Features include:
• Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 66.66MHz operation
• Burst and non-burst devices
• 16-bit byte-addressable data bus
• 30-bit address
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
– 256 Wait States for non-burst

– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping
• External DMA Slave Support
• External master interface
– Write posting from external master
– Read prefetching on PLB for external master reads
– Bursting capable from external master
– Allows external master access to all non-EBC PLB slaves
– External master can control EBC slaves for own access and control
Ethernet Controller Interface
Ethernet support provided by the PPC440EP interfaces to the physical layer but the PHY is not included on the
chip:
• One to two 10/100 interfaces running in full- and half-duplex modes
– One full Media Independent Interface (MII) with 4-bit parallel data transfer
– Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer
– Two Serial Media Independent Interfaces (SMII)
– Packet reject support
DMA to PLB3 Controller
This DMA controller provides a DMA interface between the OPB and the 64-bit PLB.
Features include:
• Supports the following transfers:
– Memory-to-memory transfers
– Buffered peripheral to memory transfers
– Buffered memory to peripheral transfers
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 32-byte buffer
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 32-bit addressing
• Address increment or decrement
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses

PCI Interface of The PowerPC 440 EP

PCI Interface
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices.
Reference Specifications:
• PowerPC CoreConnect Bus (PLB) Specification Version 3.1
• PCI Specification Version 2.2
• PCI Bus Power Management Interface Specification Version 1.1
Features include:
• PCI 2.2
– Frequency to 66MHz
– 32-bit bus
• PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an
external arbiter
• Support for Message Signaled Interrupts
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard discrete devices. Up to four
256MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
• Registered and non-registered industry standard discrete devices
• 32-bit memory interface with optional 8-bit ECC (SEC/DED)
• Sustainable 1.1GB/s peak bandwidth at 133MHz
• SSTL_2 logic
• 1 to 4 chip selects
• CAS latencies of 2, 2.5 and 3 supported
• DDR200/266 support
• Page mode accesses (up to eight open pages) with configurable paging policy
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Power management (self-refresh, suspend, sleep)

Internal Buses The PowerPC 440EP

Internal Buses
The PowerPC 440EP features five standard on-chip buses: two Processor Local Buses (PLBs), two On-Chip Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI bridge connect to the PLBs. The primary OPB hosts lower data rate peripherals. The secondary OPB is dedicated to USB 2.0 and DMA. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between

the processor core and the other on-chip cores.
Features include:
• PLB4
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 36-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte-enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
– 133MHz, maximum 4.25GB/s (simultaneous read and write)
– Processor:bus clock ratios of N:1 and N:2
• PLB3
– 64-bit implementation of the PLB architecture
– 32-bit address
– 133MHz (1:1 ratio with PLB 128), maximum 1.1GB/s (no simultaneous read and write)
• OPB (2)
– 32-bit data path
– 32-bit address
– 66.66MHz
• DCR
– 32-bit data path
– 10-bit address

microprocessor: 440EP PowerPC 440EP Embedded Processor

PowerPC® 440 processor core operating up to
667MHz with 32KB I-cache and D-cache with
parity checking.
• Selectable processor:bus clock ratios of N:1, N:2.
• Floating Point Unit with single- and doubleprecision
and single-cycle throughput.
• Dual bridged Processor Local Buses (PLBs) with
64- and 128-bit widths.
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) interface operating up to 133MHz with
ECC.
• DMA support for external peripherals, internal
UART and memory.
• PCI V2.2 interface (3.3V only). Thirty-two bits at
up to 66MHz.
• Programmable interrupt controller supports
interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT).
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are MII,
RMII, and SMII with packet reject.

• Up to four serial ports (16550 compatible UART).
• Two USB ports. One USB 1.1 Host interface with
on-chip PHY. One USB 2.0 Device interface, with
dedicated DMA, configured as a 1.1 on-chip PHY
or a 2.0 UTMI.
• External peripheral bus (16-bit data) for up to six
devices with external mastering.
• Two IIC interfaces (one with boot parameter read
capability).
• NAND Flash interface.
• SPI interface.
• General Purpose I/O (GPIO) interface.
• JTAG interface for board level testing.
• Boot from PCI memory, NOR Flash on the
external peripheral bus, or NAND Flash on the
NAND Flash interface.
• Available in RoHS compliant lead-free package.

MPC7448 POWERPC PROCESSOR HIGHLIGHTS mikroprosesor

The MPC7448 is the first discrete high- MPC7448 POWERPC® PROCESSOR BLOCK DIAGRAM
performance PowerPC® processor manufactured on 90 nanometer silicon-on-insulator (SOI)
process technology and continues Freescale Semiconductor’s strong legacy of providing PowerPC products with significant processing performance at very low power. The MPC7448 is designed to exceed 1.5 GHz processing performance and offers enhanced power management capabilities. Running at 1.4 GHz, the MPC7448 is expected to use less than 10 watts of power. MPC7448 processors are ideal for leading-edge computing, embedded network control and signal processing applications. Key architectural features include an MPX bus that scales to 200 MHz, 1 MB of on-chip L2 cache with support for Error Correcting Codes (ECC), and full 128-bit implementation of Freescale’s AltiVec™ technology with the added feature of supporting out-of-order transactions. The MPC7448 is pin compatible with Freescale’s MPC7447 and MPC7447A PowerPC products, offering an easy upgrade path to better system performance. Caching In
L2 cache helps keep the PowerPC processor pipeline full, enabling faster and more efficient processing—and the increase in the MPC7448’s L2 cache to 1 MB provides even greater opportunity for performance gains.

     The L2 cache is fully pipelined for two-cycle throughput in the MPC7448. It responds with an 11-cycle
load latency for an L1 miss that hits in L2 with ECC disabled and 12 cycles when ECC is enabled. In the MPC7448, as many as six outstanding cache misses are allowed between the L1 data cache and L2 bus. In addition, the MPC7448 supports a second cacheable store miss. The processors also provide cache locking to the L1 caches so that key performance algorithms and code can be locked in the L1 cache.


MPC7448 POWERPC PROCESSOR HIGHLIGHTS

CPU Speeds (internal) At least 1.5 GHz
Instructions per Clock 4 (3 + Branch)
L1 Cache (integrated) 32 KB instruction, 32 KB data
L2 Cache (integrated) 1 MB with optional ECC
Execution Units Integer(4), Floating-Point, AltiVec(4), Branch, Load/Store
Bus Protocol MPX/60x
Bus Frequency 200 MHz
Bus Interface 64-bit
Package 360 HiCTE BGA
Process Technology 90 nm silicon-on-insulator (SOI), Multi-Vt, Triple Gate Oxide,
Low-K Dielectric, 10 Year Reliability at 105°C



Compatibility and Support The MPC7448 can be a drop-in upgrade for MPC7447 and MPC7447A
processors because it is pin-for-pin compatible. In addition, as with all PowerPC processors, the MPC7448 is fully software compatible with the MPC7xxx family of processors. The Freescale family of PowerPC processors continues to enjoy the support of a broad set of operating systems, compilers and development tools from third-party vendors.

arsitektur , bus dan fungsi mikroprosesor dan mokrocontroler

Setiap komputer yang kita gunakan didalamnya pasti terdapat mikroprosesor. Mikroprosesor,
dikenal juga dengan sebutan CentralProcessing Unit (CPU) artinya unit pengolahan pusat.
CPU adalah pusat dari proses perhitungan dan pengolahan datayang  terbuat  dari  sebuah  lempengan yang disebut "chip“. Chip  sering disebut juga dengan "IntegratedCircuit (IC)",  bentuknya  kecil, terbuat  dari  lempengan silikon dan bisa terdiridari 10 juta transistor.
Mikroprosesor pertama adalah intel 4004yang dikenalkan tahun1971,  tetapi kegunaan  mikroprosesor ini masih sangat terbatas, hanya dapat digunakan untuk operasi penambahan dan pengurangan.Mikroprosesor pertama yang digunakan untuk komputer di rumah adalah intel 8080, merupakan komputer 8bit dalam satu chip yang diperkenalkan pada tahun 1974.Tahun 1979 diperkenalkanmikroprosesor baru yaitu 8088. Mikroprosesor 8088 mengalami perkembangan menjadi 80286, berkembang lagi menjadi 80486, kemudian menjadi Pentium, dari Pentium I sampai dengan sekarang,Pentium IV.

Transistor berbentuk seperti tabung yang sangat kecil, terdapatpada Chip.

Micron adalah ukuran dalam Micron (10 pangkat -6), merupakan kabelterkecil dalam Chip

Clock Speed = kecepatan maksimal sebuah prosesor

Data width = lebar dari Arithmatic Logic Unit (ALU) / Unitpengelola aritmatika, untuk proses pengurangan, pembagian, perkalian dansebagainya.

MIPS = Millions of Instructions Per Second / Jutaan perintah perdetik.

fungsi pin pada mikroprosesor

n  AD15-AD0 Sebagia addressmultiplexer dimana (ALE=1) /data bus(ALE=0).

n  A19/S6-A16/S3(multiplexed) Sebagai 4 bit terakhir dengan 4 bits dari 20-bit address A16 s/dA19 Atau status bits S6- S3.

n  M/IO Sebagai indikasi apakahalamar memory atau alamat Input Output.

n  RD Ketika 0, data busmenujukan pembacaraan dari memory atau dari I/O device.

n  WR Berfungsi kepadamikroproses untuk menunjuk ke memory atau I/O device melalui data bus. Jika 0,maka data bus telah valid data.

n  ALE (Address latchenable) Ketika 1, address data bus melakukan penulisan pada memory atauI/O address.

n  DT/R (DataTransmit/Receive) Data bus sebagai transmitting/receiving data.

n  DEN (Data bus Enable) mengerakkan data bus diluar buffer.

n  S7: Logic 1, S6: Logic0.

n  S5: Jika tidak ada flagbits, dimana hanya untuk alamat yang sesuai denngan kondisinya

n  S4-S3: Memberikan status padasegment saat akses selama mengunakan power.

n  S2, S1, S0: Mengindikasi fungsi buscycle (decoded by 8288).

CONT.

n  INTR (Interrupt Request)Ketika INTR=1 dan IF=1, maka mikroprosesor menyediakannya service interrupt.INTA kembali aktif seletah intruksinya lengkap.

n  INTA (InterruptAcknowledge) mikroprosesor merespon pada INTA. Karena tabel vektor dapattepisah dan akan menuju data bus.

n  NMI (Non-maskableinterrupt) Fungsi seperti INTR, Jika flag bit tidak disetujui, dan jugaberfungsi sebagai intrupsi pada vektor 2.

n  CLK (Clock) inputmempunyai duty cycle of 33% (high for 1/3 and low for 2/3s)

n  VCC/GND Power supply(5V) and GND (0V).

n  MN/ MX untuk modeminimum (5V) atau mode maximum (0V) secara operasi.

n  BHE (Bus High Enable). Mengaktifkansebagian data bus yang sangat penting (D15 -D 8 ) selama operasi pembacaan danpenulisan.

n  READY melakukan prosestunggu yang telah ditetapkan (pengontrolan memori dan I/O pada proses pembacaanatau penulisan) oleh mikroprosesor.